1. Technical Field
The present disclosure relates to an improved die attaching method.
2. Description of the Related Art
A wafer fabrication process may form integrated circuits in or on a semiconductor wafer. An electrical die sorting (EDS) test may sort semiconductor dies into good or reject ones. A wafer sawing process may divide a semiconductor wafer into individual semiconductor dies. A package assembly process may produce a semiconductor chip package using good dies.
Typical wafers may experience an inking process for inking reject dies after an EDS test. Alternatively, inkless wafers may be sorted using wafer map data available from the EDS test. Therefore, inkless wafers may not need an inking process and an inking mark reading process.
Instead, inkless wafers may require a matching process for matching a wafer with wafer map data. The matching process may search a wafer for a first die to be picked up. For example, the matching process may match a first die of an actual wafer with a first die of wafer map data. If a first die of wafer map data is mismatched with a first die of an actual wafer, a die attaching process may be performed incorrectly.
A conventional die attaching method may include a reference die searching method and a row/column chip counting method.
FIG. 1 is a plan view of a wafer 10 having a plurality of semiconductor dies 11 used in a conventional die attaching process using a reference die searching method. FIG. 2A is an enlarged view of section A in FIG. 1. FIG. 2B is an enlarged view of section B in FIG. 1.
Referring to FIGS. 1 to 2B, a wafer 10 may have mirror semiconductor dies 13 (e.g. semiconductor dies without integrated circuits) at two or three edge points thereof. A reference die searching method may recognize chip patterns (P1, P2) near the mirror semiconductor dies 13 to search for a first die 11a. 
The mirror semiconductor die 13 may negatively impact production rate of a wafer 10, particularly a wafer having small-sized semiconductor dies. For example, a semiconductor die having a size of 3 mm or less may be liable to a first die search error that may result from the difference between expansion rate of a center area and expansion rate of an edge area on expanding a wafer carrier tape.
FIG. 3 is a plan view of a part of a wafer 30 used in a conventional die attaching process using a row/column chip counting method.
Referring to FIG. 3, the wafer 30 does not have mirror semiconductor dies. A row/column counting method may recognize chip patterns of the wafer 30 to measure the number of semiconductor dies 31, and match the actual number of semiconductor dies 31 of the wafer 30 with the number of semiconductor dies of wafer map data to search for a first die 31a. 
However, if a semiconductor die 35 has chip patterns formed outside a good chip area, the row/column chip counting method may be liable to a chip count error. As a result, the actual number of semiconductor dies on row and column may be mismatched with the number of semiconductor dies on wafer map data.
The conventional die attaching method may not consider positional changes of semiconductor dies which may occur during a tape attaching process and/or a wafer sawing process on matching a first die of a wafer after tape expansion with a first die of wafer map data available from an EDS test, thus resulting in a first die search error. A chip count error during a die attaching process may lead to numerous reject dies being packaged as a good die.